1. Field of the Invention
The present invention relates to a substrate voltage generator in a semiconductor memory device, and more particularly to a charge pump circuit of the substrate voltage generator.
2. Description of the Related Art
All MOS memory architectures on occasion use on-chip voltage generation. While any voltage between ground and the power supply is available on a memory chip, it is also possible to generate on the chip voltages that are below ground and above the power supply value.
The most common on-chip voltage generation in MOS memories is back-bias voltage generation. Early MOS RAMs used a power supply which provided a negative voltage bias to the substrate. On-chip back-bias generation has replaced one of these power supplies in many cases.
The most important advantage of the on-chip substrate voltage generator was the reduced probability of localized forward biasing of junctions. Such forward biasing injects electrons into the substrate leading to dynamic circuit problems and, in memory devices, for example, reduced refresh times due to a collection of electrons beneath the memory storage capacitor plate for stored `ones`.
Speed and power characteristics also improve when an on-chip substrate voltage generator is used because transistors operate in a flatter part of the body-effect curve and so lose less drive capability as their sources rise and because the lower junction capacitance reduces the load.
Thus, the variation of a threshold voltage caused by the body effect of a transistor is minimized and the punch-through voltage is increased.
Another advantage is that the specific bit-line capacitance (Cb/Cs ratio) improves because junction capacitances contribute more to bit line capacitance (Cb) than to the total storage capacitance (Cs) so that a differential signal to sense amplifiers will increase.
Therefore, if a constant negative voltage is supplied to the substrate by the use of the substrate voltage generator, the performance of the memory chip is improved.
A conventional substrate voltage generator is illustrated in FIG. 1. The substrate voltage generator of FIG.1 includes an oscillator 1, a driver 2, a charge pump circuit 3 and a detector 4.
Because an output signal .PHI.en from detector 4 is applied to oscillator 1 by way of a feedback loop (as shown), oscillator 1 is only operational when a detected substrate voltage V.sub.BB from terminal V.sub.BB, which is coupled to a semiconductor substrate (not shown), does not maintain a constant negative voltage.
Driver 2 supplies rectangular wave signal 9 to charge pump capacitor 5 in charge pump circuit 3 derived from an alternating current (ac) signal 8 generated from oscillator 1.
Charge pump circuit 3 is connected to substrate voltage V.sub.BB and includes one charge pump capacitor 5, and two diodes 6, and 7. The voltage level to which charge pump capacitor 5 is charged is determined by the amplitude of the rectangular wave signal 9 supplied thereto.
When rectangular wave signal 9 (shown as clock signal CLK) is at logic "high", diode D.sub.GND is turned on and charges thereto are discharged to ground.
Conversely, when rectangular wave signal 9 (clock CLK) is at logic "low", diode D.sub.SUB is turned on and charges thereto are transferred away from the substrate voltage terminal. As a result, the substrate bias voltage V.sub.BB goes to a negative voltage level.
A more complex conventional circuit diagram for a charge pump circuit, operated on by CLK1 to CLK4, is shown in FIG. 2A and consists of P-channel MOS transistors. Charge pump circuit 3' shown in FIG. 2A can be substituted for the simpler charge pump circuit 3 of FIG. 1.
Charge pump circuit 3' is coupled to a driver circuit 2' (see FIG. 2B), which driver circuit 2' generates additional clock signals CLK1-CLK4 (derived from clock signal (CLK)) to be received by charge pump circuit 3'.
Driver circuit 2' may receive clock signal CLK from a driver 2, which driver 2 generates a rectangular wave (clock) signal in response to an oscillator (ac) signal substantially as provided in block form in FIG. 1. It should be readily apparent, however, that any and all equivalent clocking schemes may be equally appropriate and substituted for the one indicated. FIG. 3 shows a timing chart for the conventional charge pump circuit shown in FIG. 2A.
The operation of charge pump circuit 3' will now be described with reference to FIG. 2A and FIG. 3. For descriptive convenience, it is assumed that the MOS transistors in FIG. 2A are ideal transistors, and therefore, the threshold voltages of these MOS transistors will not be considered.
Clocks CLK1 and CLK2 are transmitted from driver circuit 2' so as to be in-phase but so as to have different pulse widths from one another.
Similarly, clocks CLK3 and CLK4 are also provided from driver circuit 2' and have the same phase but different pulse widths from one another.
In addition, the phase of clocks CLK1 and CLK2 is such that the phase is opposite from the phase of clocks CLK3 and CLK4. As a result, charge pump circuit 3' of FIG. 2A is capable of performing pump operations twice during a complete clock cycle.
When clocks CLK1 and CLK2 become logic "high" corresponding to high power voltage V.sub.CC level, then clocks CLK3 and CLK4 become logic "low" with ground voltage V.sub.SS level--after the lapse of a predetermined time.
At such time, voltages at nodes c and d are set to a negative power voltage -V.sub.CC level by third and fourth pump capacitors 13 and 14. In turn, third and fifth transistors 23 and 25 turn on.
Charges which flowed to node b from substrate voltage terminal V.sub.BB during a previous half period are grounded through third transistor 23.
Similarly, at node c, because charges flow from substrate voltage terminal V.sub.BB through fifth transistor 25, which is turned on, the voltage level at substrate voltage terminal V.sub.BB drops to a more negative voltage level.
Because the voltage at node b exceeds ground voltage V.sub.BB level, sixth transistor 26 turns off so as to electrically isolate substrate voltage terminal V.sub.BB from ground.
When clocks CLK3 and CLK4 become logic "high", clocks CLK1 and CLK2 go logic "low" because nodes a and b are lowered to negative power voltage -V.sub.CC level by first and second pump capacitors 11 and 12. In turn, second and sixth transistors 22 and 26 turn on.
Charges which flowed to node c from substrate voltage terminal V.sub.BB during a previous half clock cycle are grounded through sixth transistor 26.
Similarly, as charges flow to node b through second transistor 22 which is turned on, substrate voltage terminal V.sub.BB drops to a negative voltage.
At this point in time, because the voltage at node c exceeds ground voltage V.sub.SS level, third transistor 23 turns off to electrically isolate substrate voltage terminal V.sub.BB from ground.
In this circuit configuration, it is important that neither second and third transistors 22, 23 nor fifth and sixth transistors 25, 26 be simultaneously turned on.
When both second and third transistors 22, 23 or fifth and sixth transistors 25, 26 are simultaneously turned on, because substrate voltage terminal V.sub.BB is connected to ground, substrate voltage terminal V.sub.BB cannot be made to drop to a negative voltage level.
Consequently, the fact that second and third transistors 22, 23 (or, fifth and sixth transistors 25, 26) are such that they can be simultaneously switched on, is a serious drawback.
More specifically, as power voltage V.sub.CC level drops in response to a powering-up, the power of the memory chip is turned on to raise the power voltage V.sub.CC level. At this point, the voltage at nodes a to d drops to a negative power voltage -V.sub.CC level in response to first to fourth pump capacitors 11 to 14.
In turn, because the voltage level at substrate voltage terminal V.sub.BB has not been set to a negative voltage level, first and fourth transistors 21 and 24, having their respective gates connected to substrate voltage terminal V.sub.BB, are necessarily turned off.
In addition, second and sixth transistors 22 and 26 are turned on by voltage levels at nodes a and b. Similarly, third and fifth transistors 23 and 25 are turned on by voltage levels at nodes c and d.
Because second and third transistors 22 and 23, and fifth and sixth transistors 25 and 26, are simultaneously turned on, substrate voltage terminal V.sub.BB becomes grounded; and, the voltage thereto cannot be made negative, as intended.
To overcome this initial drawback, a power voltage V.sub.CC level of considerable magnitude must necessarily be applied.
However, when substrate voltage terminal V.sub.BB is eventually set to a negative voltage level using a high magnitude power voltage V.sub.CC level, an oscillator 1 connected thereto must necessarily also operate at this high power voltage level. As a result, standby current is abruptly increased.
FIG. 6 shows a set up characteristic curve for the substrate voltage terminal V.sub.BB using the charge pump circuit of FIG. 2A where power voltage V.sub.CC level is successively raised and then dropped.
During the first cycle, where power voltage V.sub.CC level is raised, substrate voltage terminal V.sub.BB goes to a negative voltage level at an input power voltage V.sub.CC level of about 2 volts.
However, in a subsequent cycle, as power voltage V.sub.CC level is raised from 0 volts, substrate voltage terminal V.sub.BB goes to a negative voltage level at an input power voltage V.sub.CC level of 4 volts or greater. As such, it is clear that because substrate voltage terminal V.sub.BB goes negative for high voltage levels of V.sub.CC, stand-by current increases.
Furthermore, in connection with charge pump circuit 3' of FIG. 2A, because the potential at nodes b and c connected to third and sixth transistors 23 and 26 is not constant, charge pumping efficiency is significantly lowered.
Stated differently, as charges are passed to ground from substrate voltage terminal V.sub.BB, because the potential at nodes b and c cannot be maintained at a negative power voltage -V.sub.CC level, but instead, the respective node potential go to levels which exceed the negative power voltage level of -V.sub.CC, sufficient and rapid discharge is not possible and charge pumping efficiency is degraded.